Seoul team reports a chip that can slow light on demand

On 17 July 2026, researchers at Seoul National University announced that computer simulations of a new optical chip architecture had reproduced real-time control over the speed of light passing through the device, a result that, if borne out in hardware, would push photonics into territory long treated as fixed by the laws of solid-state physics. The work was led by Professors Namkyoo Park and Sunkyu Yu of the Department of Electrical and Computer Engineering at the university's College of Engineering, according to a release carried by Phys.org.

The claim sits at the intersection of two pressures now shaping Asian semiconductor strategy: the global race to find alternatives to silicon's bandwidth ceiling, and the steady South Korean push to move up the photonics value chain beyond memory chips into the more specialised optical-component layer that today is dominated by US and Japanese vendors.

What the team actually built

The Seoul group did not report a finished commercial device. The announcement describes a chip-level architecture whose optical response can be tuned while light is still inside the waveguide, allowing the group velocity of a pulse to be modulated on the fly. In practical terms, that means the same chip could act as a delay line at one moment and a fast-pass filter at another, without swapping hardware. For data-centre operators, a tunable optical delay is the kind of primitive that reduces the need for buffers in all-optical switching fabrics, which are widely seen as the next bottleneck for machine-learning traffic.

The work is, for now, a simulation result rather than a fabricated prototype. That distinction matters. Photonic claims of this kind have a track record of compressing nicely into a finite-element model and then collapsing against the noise floor of a real fab. The Seoul team's next milestone, on which their credibility will rest, is a measurable device in silicon photonics or a compatible platform, with on-chip characterisation published alongside the simulation.

Why the claim is unusual

Group velocity in a passive dielectric waveguide is essentially set by geometry and material index. You can slow light through resonant structures, or speed it through band engineering, but doing both with the same hardware in a single operating envelope is not standard. The Korean group's framing, as reported, is that the architecture's response can be reconfigured dynamically, which is closer to a tunable metamaterial than to a conventional strip waveguide.

Independent photonics researchers contacted about the work in past reporting cycles have generally taken the line that extraordinary claims in this corner of the discipline require extraordinary fabrication evidence: a published wafer, a measured S-parameter, a published eye diagram. None of that has appeared yet. The university release, and the Phys.org write-up that drew from it, frame the result as a step toward programmable optical computing rather than as a deployable component.

The structural frame

Read against the wider map, the announcement is one more data point in the slow unbundling of the optical stack. For three decades the centre of gravity in photonics has sat in the United States and Japan, with compound-semiconductor foundries in California, Massachusetts and the Kanto region handling the III-V epitaxy and packaging that silicon fabs cannot do themselves. South Korea's industrial record in memory and logic gives Seoul's academic groups a structural advantage: they can iterate against an installed base of mature process lines, and they can borrow mask sets and packaging IP from the chaebol ecosystem without negotiating fresh export licences.

That advantage is not unique to Seoul. Comparable photonics work is coming out of Tsinghua and the Chinese Academy of Sciences' Institute of Semiconductors, where silicon-photonics groups have published tunable-delay architectures of their own. The competitive question, then, is not whether tunable optical delay is feasible but who can integrate it into a working transceiver first and lock in the IP. The Seoul announcement arrives without a patent filing in evidence, which leaves room for a parallel Chinese filing on similar ground; sources do not confirm whether one exists.

What to watch next

Three things will determine whether the result becomes a benchmark or a footnote. First, a fabricated prototype with published measurement data, ideally in a foundry-compatible silicon photonics process. Second, an application demonstration: an all-optical buffer, a tunable dispersion compensator, or a feed-forward neural layer where the delay is part of the algorithm. Third, a defensible IP position, through patent filing or publication priority, against the Chinese groups working in adjacent territory.

The sources do not specify any of those milestones by date, nor do they give a fabrication partner or a commercialisation pathway. What they do establish is that a credible Korean academic team is now publicly working on the problem at the chip scale, and that the result, if it survives the trip from simulation to silicon, would land on a market segment where incumbents are heavily concentrated and where a Korean entrant would face a familiar but navigable set of US export-control headwinds. The honest read for now is that the announcement is a research marker, not a product. The interesting question is the second one.

This article treats the Seoul National University announcement as a simulation-stage research claim rather than a deployable technology, and reads it against the wider contest over photonics IP across Northeast Asia.